3 LCD%26;amp;VGA控制器设计
设计行场扫描时序,一般有两种方式:查找表方式和编程逻辑方式。查找表方式主要由存储芯片构成,如SRAM、EPROM、PORM等。使用时,先根据所要产生的时序在存储单元写入相应的数值,查表时再从表内读出时应存储单元的数值,以形成扫描时序。扫描时序查找表分为行扫描时序查找表和场扫描时序查找表。场扫描时序查找表的输入时钟由行同步脉冲提供。用查找表形成时序的方法存在体积大、计算烦琐的缺点。随着大规模逻辑芯片的出现,利用编程逻辑方法产生行场扫描时序是一个发展方向。这种方法具有电路简单、功能强、修改方便、可靠性高等优点。图3为LCD控制器的框图。
在本设计中,点时钟DCLK由处理器DSP的系统时钟40MHz经数字锁相环二分频得到。点时钟驱动行时序生成器,产生图2所示的行同步信号HS和行消隐信号HB。为避免毛刺,控制器设计采用同步设计方法,如图3所示,行同步信号HS通过一个微分电路,产生一个点时钟周期宽的场时序生成器使能信号。在使能信号有效时,场时序生成器开始计数,并产生场同步信号VS和场消隐信号VB。行消隐信号HB和场消隐信号VB相与后即为数据使能信号DATA_EN。该数据使能信号作为产生帧存地址计数器的计数使能,以保证DATA_EN信号为高时,将象素送给AMLCD显示。在DCLK的上升沿,帧存地址计数器加一,帧存SRAM经过一段延时后,象素数据出现在总线上。在DCLK的下降沿AMLCD将数据读入。该LCD控制器的设计方法很容易用于VGA视频接口。在VGA接口电路的设计中,不需点时钟电路,只须将行同步信号与场同步信号输出,将数据使能信号作为复合消隐信号输入即可。产生行场扫描时序的VHDL描述如下:
entity seq_gen is port(clk_seq : in std_logic; rst_seq : in std_logic; LCD_hs_out : out std_logic; lcd_dataen : out std_logic; lcd_vs_out : out std_logic; pix_clk : out std_logic ); end seq_gen; architecture rtl_seq_gen of seq_gen is signa
l lcd_hb : std_logic; signal lcd_hs : std_logic; signal lcd_vb : std_logic; signal lcd_vs : std_logic; signal clken_vcount : std_logic; begin hcount: block signal hcountreg :std_logic_vector(9 downto 0); signal hz_temp : std_logic; signal lcd_hz : std_logic; begin process (clk_seq,lcd_hz) begin if (lcd_hz = "1") then hcountreg <= (others =>"0"); elsif clk_seq"event and clk_seq = "1" then hcountreg <= hcountreg +1; end if; end process; lcd_hb <= "0" when hcountreg >=600 and hcount
reg < 650 else "1"; lcd_hs <="0" when hcountreg >=610 and hcountreg < 630 else "1"; hz_temp <= "1" when hcountreg = 650 else "0"; lcd_hz <=hz_temp or rst_seq; end block hcount; diff : block signal inputrega : std_logic; signal inputregb : std_logic; begin process(clk_seq) begin if clk_seq"event and clk_seq="1" then inputregb <= inputrega; inputrega <= not lcd_hs; end if; end process; clken_vcount <= not inputregb and inputrega; end block diff; vcount : block signal vcountreg : std_logic_vector(9 downto 0); signal vz_temp : std_logic; signal lcd_vz : std_logic; begin process (clk_seq,lcd_vz) begin if(lcd_vz="1")then vcountreg <= (others => "0"); elsif clk_seq"event and clk_seq = "1" then if clken_vcount = "1" then vcountreg <= vcountreg +1; end if; end if; end process; lcd_vb <= "0" when vcountreg >=600 and vcountreg < 615 else "1"; lcd_vs <="0" when vcountreg >=607 and vcounreg < 610 else "1"; vz_temp <= "1" when vcountreg = 615 else "0"; lcd_vz <= vz_temp or rst_seq; end block vcount; pix_clk <=clk_seq; lcd_dataen <=lcd_hb and lcd_vb; lcd_hs_out <=lcd_hs; lcd_vs_out <=lcd_vs; end rtl_seq_gen; 这种用VHDL产生扫描时序的方法简单、易读,并且易于修改。在代码中只须修改一些时序参数就能产生任意时序的波形,具有很好的可重用性。